The present invention relates to a nonvolatile semiconductor memory device and more particularly relates to a nonvolatile semiconductor memory device like a flash memory including a differential sense amplifier.
Recently, a nonvolatile semiconductor memory device has been increasingly required to operate at higher and higher speeds. To meet such a demand, the application of a folded bit line arrangement, which is usually used for a dynamic random access memory (DRAM), has been proposed as an effective means for realizing such a high-speed operation. In the folded bit line arrangement, a bit line and its associated dummy bit line are connected in parallel to a sense amplifier. In this arrangement, reading is performed by comparing information stored in a memory cell connected to the bit line to reference information stored in an associated dummy cell connected to the dummy bit line and by amplifying a voltage difference therebetween. The arrangements of this type are disclosed in Japanese Laid-Open Publications Nos. 6-290591 and 8-203291, for example.
These folded bit line arrangements are superior to conventional opened bit line arrangements in terms of noise resistance and low power dissipation, and therefore applicable particularly effectively to circuits that should operate at higher speeds.
The present inventors analyzed the operation of a nonvolatile semiconductor memory device with the known folded bit line arrangement from various angles to find that the device of this type also has several shortcomings. Specifically, a device with the known folded bit line arrangement cannot read data from a desired memory cell accurately and rapidly enough, because there is capacitance imbalance between a bit line and its associated dummy bit line in reading out the data.
FIG. 7 illustrates a circuit configuration for a nonvolatile semiconductor memory device with the folded bit line arrangement as disclosed in Japanese Laid-Open Publication No. 8-203291 identified above. As shown in FIG. 7, the device includes sense amplifier 30, bit line BL and its complementary bit line BLB. One end of the bit line BL is connected to the sense amplifier 30 via a transfer gate 33, while the other end thereof is connected to a pre-charging transfer gate 11P. One end of the complementary bit line BLB is connected to the sense amplifier 30 via a transfer gate 34, while the other end thereof is connected to a pre-charging transfer gate 21P. First and second memory cell blocks 110a and 120a are connected to the bit line BL and the complementary bit line BLB by way of first and second select gates 11S and 22S, respectively.
The first memory cell block 110a consists of four memory cells M11a, M12a, M13a and M14a, which are connected in series together and to word lines WL1a, WL2a, WL3a and WL4a, respectively. The second memory cell block 120a also consists of four memory cells M21a, M22a, M23a and M24a, which are connected in series together and also connected to the word lines WL1a, WL2a, WL3a and WL4a, respectively. Third and fourth memory cell blocks 110b and 120b with the same configurations as the first and second memory cell blocks 110a and 120a are connected to the bit line BL and the complementary bit line BLB via third and fourth select gates 12S and 23S, respectively.
Furthermore, a first dummy cell block 110D with the same configuration as the first memory cell block 110a is connected to the bit line BL via a first dummy select gate 11D. And a second dummy cell block 120D with the same configuration as the first dummy cell block 110D is connected to the complementary bit line BLB via a second dummy select gate 21D.
Hereinafter, it will be briefly described how the nonvolatile semiconductor memory device with such an arrangement performs reading.
For example, suppose information should be read out from the memory cell M14b in the third memory cell block 110b. In such a case, reference information (i.e., a reference potential) is supplied from the dummy cells M21D and M22D to the sense amplifier 30. In the following example, the memory cell M14b is now being written, i.e., the threshold voltage of the memory cell M14b is between 1 and 2 V and the drain-source current thereof is about 80 .mu.A. It should be noted that a memory cell is erased when a threshold voltage thereof is 8 V or more and the drain-source current thereof is 0 .mu.A. On the other hand, the reference information stored in the dummy cells M21D and M22D, for example, is supposed to be average between a memory cell being erased and a memory cell being written.
First, the bit line BL and the complementary bit line BLB are pre-charged to a potential, which may be half of a supply potential V.sub.DD, by way of the pre-charging transfer gates 11P and 21P, respectively. Thereafter, the word line WL4b connected to the control gate of the memory cell M14b is activated and a high-level select signal SG2 is applied to the gate of the third select gate 12S to turn the gate 12S ON. In this manner, the information is sent out from the memory cell 14b onto the bit line BL. In this case, capacitance caused by the third memory cell block 110b is applied to the bit line BL. At the same time, since the high-level select signal SG2 also turns the second select gate 22S ON, capacitance caused by the second memory cell block 120a is applied to the complementary bit line BLB.
On the other hand, the dummy cells M21D and M22D generate the reference potential to read the information from the memory cell M14b. In this case, dummy word lines DWL1 and DWL2 connected to the respective control gates of the dummy cells M21D and M22D are activated and a high-level dummy select signal DSG2 is applied to the gate of the second dummy select gate 21D to turn the gate 21D ON. In this manner, the reference information is transferred from the dummy cells M21D and M22D to the complementary bit line BLB. In this case, capacitance caused by the second dummy cell block 120D is applied to the complementary bit line BLB by way of the second dummy select gate 21D.
FIG. 8 schematically illustrates respective capacitance components applied to the bit line BL and the complementary bit line BLB while the semiconductor memory device shown in FIG. 7 is reading data. In FIG. 8, the same members as those illustrated in FIG. 7 are identified by the same reference numerals. As shown in FIG. 8, when a memory cell connected to the bit line BL is accessed, the sense amplifier 30 senses the line and diffusion capacitance CBL caused by the bit line BL and the capacitance C110b caused by the third memory cell block 110b from the bit line BL. The sense amplifier 30 also senses the line and diffusion capacitance CBLB caused by the complementary bit line BLB, the capacitance C120a caused by the second memory cell block 120a and the capacitance C120D caused by the second dummy cell block 120D from the complementary bit line BLB. In this case, the capacitance C110b or C120D includes the diffusion capacitance components of respective cells and the line capacitance caused by a sub-bit line when the drain of each cell is connected to the select gate.
As can be seen from FIG. 8, the capacitance applied to the bit line BL is different from that applied to the complementary bit line BLB during reading. For example, supposing each of the second and third memory cell blocks 120a and 110b and the second dummy cell block 120D consists of the same number of memory cells, the capacitance CBL applied to the bit line BL is not greatly different from the capacitance CBLB applied to the complementary bit line BLB. Thus, extra load capacitance, i.e., the capacitance C120D caused by the dummy cell block 120D, is applied to the complementary bit line BLB and seriously affects a read time.
In performing a readout operation using the differential sense amplifier 30, the charges stored on the bit line BL and the complementary bit line BLB are discharged with cell currents flowing through the memory cell 14b and the cell current flowing through the dummy cells M21D and M22D, respectively. As a result, a potential difference is created between the bit line BL and the complementary bit line BLB and then amplified using the amplifier 30.
In this case, a potential variation on the complementary bit line BLB, to which the dummy cells M21D and M22D are connected, is preferably a median between a potential variation on the bit line BL, to which a memory cell being erased is connected, and a potential variation on the bit line BL, to which a memory cell being written is connected. For example, suppose a constant cell current flows through the memory cell M14b and a cell current flowing through the dummy cells M21D and M22D is half of the cell current flowing through the memory cell M14b. And also suppose the load capacitances applied to the bit line BL and the complementary bit line BLB are equal to each other. In that case, a potential variation .DELTA.V after a predetermined time .DELTA.t has passed since the start of discharge is given by the following Equation 1 by modifying a relationship I=C(dV/dt): EQU .DELTA.V=(.DELTA.t/C).multidot.I (1)
where V, I, C and t represent voltage, current, capacitance and time, respectively.
Equation 1 shows that the potential variation .DELTA.V is inversely proportional to the capacitance C and that the time-dependent variation .DELTA.t is proportional to the capacitance C. As also can be seen from Equation 1, if the additional load capacitance C120D is applied to the complementary bit line BLB, then a read time, i.e., a time taken to cause a predetermined potential variation on the complementary bit line BLB, increases.
FIG. 9 illustrates discharge waveforms of the circuit shown in FIG. 8. In FIG. 9, the axis of abscissas represents time, while the axis of ordinates represents potentials on the bit line BL. VPC represents a pre-charge potential, which is equal to 1/2 V.sub.DD. As shown in FIG. 9, since a predetermined drain-source current flows through a memory cell being written as indicated by "1", its potential decreases with time. In contrast, since no drain-source current flows through a memory cell being erased as indicated by "0", its potential does not decrease with time. In FIG. 9, the reference potentials Vref0, Vref1 and Vref2 represent the waveforms of discharge where the dummy cells M21D and M22D are connected to the complementary bit line BLB. Specifically, Vref0 represents an ideal state, Vref1 represents a situation where a high load capacitance C120D is applied and Vref2 represents a situation where a low load capacitance C120D is applied. As can be seen from FIG. 9, if the load capacitance C120D is applied, the waveform of discharge of the complementary bit line BLB deviates from the ideal waveform Vref0 of discharge. This is because a capacitance imbalance is caused between the bit line BL and the complementary bit line BLB. In such a situation, the ideal reference potential Vref0 cannot be generated and it takes an additional time to cause a predetermined potential variation required for reading. As a result, reading cannot be performed at sufficiently high speeds.